View STK16C88-WF45I_8589267.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

stk16c88 256-kbit (32 k 8) autostore+ nvsram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-50595 rev. *c revised february 27, 2012 256-kbit (32 k 8) autostore+ nvsram features 25 ns and 45 ns access times directly replaces battery-backed sram modules such as dallas/maxim ds1230 ab automatic nonvolatile store on power loss nonvolatile store under software control automatic recall to sram on power up unlimited read/write endurance unlimited recall cycles 1,000,000 store cycles 100 year data retention single 5 v + 10% power supply commercial and industrial temperatures 28-pin (600 mil) pdip package rohs compliance functional description the cypress stk16c88 is a 256 kb fast static ram with a nonvolatile element in each memory cell. the embedded nonvolatile elements incor porate quantumtrap technology producing the world?s most reliable nonvolatile memory. the sram provides unlimited read and write cycles, while independent, nonvolatile data resides in the highly reliable quantumtrap cell. data transfers from the sram to the nonvolatile elements (the store operation) takes place automatically at power down. on power up, data is restored to the sram (the recall operation) from the nonvolatile memory. both the store and recall operations are also available under software control. logic block diagram not recommended for new designs. in production to support ongoing production programs.
stk16c88 document number: 001-50595 rev. *c page 2 of 17 contents pin configurations ........................................................... 3 pin definitions .................................................................. 3 device operation .............................................................. 4 sram read ................................................................ 4 sram write ................................................................. 4 autostore+ operation .................................................. 4 hardware recall (power up) ................................... 4 software store ......................................................... 4 software recall ....................................................... 4 hardware protect ........................................................ 4 noise considerations .................................................. 5 low average active power .... ..................................... 5 best practices ................................................................... 5 maximum ratings ............................................................. 7 operating range ............................................................... 7 dc electrical characteristics .......................................... 7 data retention and endurance ....................................... 8 capacitance ...................................................................... 8 thermal resistance .......................................................... 8 ac test loads .................................................................. 8 ac test conditions .......................................................... 8 ac switching characteristics ? sram read cycle ...... 9 switching waveforms ? sram read cycle ................... 9 ac switching characteristics ? sram write cycle .... 10 autostore or power up recall .................................. 11 software controlled store/recall cycle ................ 12 ordering information ...................................................... 13 ordering code definitions ..... .................................... 13 package diagram ............................................................ 14 acronyms ........................................................................ 15 document conventions ................................................. 15 units of measure ....................................................... 15 document history page ................................................. 16 sales, solutions and legal information ....................... 17 worldwide sales and design s upport ......... .............. 17 products .................................................................... 17 psoc solutions ......................................................... 17 not recommended for new designs. in production to support ongoing production programs.
stk16c88 document number: 001-50595 rev. *c page 3 of 17 pin configurations figure 1. 28-pin pdip pinout a 14 a 12 a 7 a 6 dq 0 dq 1 dq 2 a 3 a 2 a 1 a 13 a 8 a 9 a 11 a 10 dq 7 dq 6 v ss a 0 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ce a 5 a 4 28 27 26 25 v cc we dq 5 dq 3 dq 4 oe (top) pin definitions pin name alt i/o type description a 0 ?a 14 input address inputs. used to select one of the 32,768 bytes of the nvsram. dq 0 ?dq 7 input or output bidirectional data i/o lines . used as input or output lines depending on operation. we w input write enable input, active low . when the chip is enabled and we is low, data on the i/o pins is written to the specific address location. ce e input chip enable input, active low . when low, selects the chip . when high, deselects the chip. oe g input output enable, active low . the active low oe input enables the data output buffers during read cycle s. deasserting oe high causes the i/o pins to tristate. v ss ground ground for the device . the device is connected to ground of the system. v cc power supply power supply inputs to the device . not recommended for new designs. in production to support ongoing production programs.
stk16c88 document number: 001-50595 rev. *c page 4 of 17 device operation the autostore+ stk16c88 is a fast 32k x 8 sram that does not lose its data on power down. the data is preserved in integral quantumtrap nonvolatile storage elements when power is lost. automatic store on power down and automatic recall on power up guarantee data integrit y without the use of batteries. sram read the stk16c88 performs a read cycle whenever ce and oe are low while we is high. the address specified on pins a 0?14 determines the 32,768 data bytes accessed. when the read is initiated by an address transition, the outputs are valid after a delay of t aa (read cycle 1). if the read is initiated by ce or oe , the outputs are valid at t ace or at t doe , whichever is later (read cycle 2). the data outputs repeatedly respond to address changes within the t aa access time without the need for transitions on any control input pins, and remains valid until another address change or until ce or oe is brought high. sram write a write cycle is performed whenever ce and we are low. the address inputs must be stable prior to entering the write cycle and must remain stable until either ce or we goes high at the end of the cycle. the data on the common i/o pins dq 0?7 are written into the memory if it has valid t sd , before the end of a we controlled write or before the end of an ce controlled write. keep oe high during the entire write cycle to avoid data bus contention on common i/o lines. if oe is left low, internal circuitry turns off the output buffers t hzwe after we goes low. autostore+ operation the stk16c88?s automatic store on power down is completely transparent to t he system. the store initiation takes less than 500 ns when power is lost (v cc < v switch ) at which point the part depends only on its internal capacitor for store completion. if the power supply drops faster than 20 ? s/volt before vcc reaches vswitch, then a 2.2 ohm resistor should be inserted between vcc and the system supply to avoid a momentary excess of current between vcc and internal capacitor. in order to prevent unneeded store operations, automatic stores are ignored unless at least one write operation has taken place since the most recent store or recall cycle. software initiated store cycles are performed regardless of whether or not a write operation has taken place. hardware recall (power up) during power up or after any low power condition (v cc stk16c88 document number: 001-50595 rev. *c page 5 of 17 noise considerations the stk16c88 is a high speed memory. it must have a high frequency bypass capacitor of approximately 0.1 f connected between v cc and v ss, using leads and traces that are as short as possible. as with all high speed cmos ics, careful routing of power, ground, and signals reduce circuit noise. low average active power cmos technology provides the stk16c88 the benefit of drawing significantly less current when it is cycled at times longer than 50 ns. figure 2 and figure 3 shows the relationship between i cc and read or write cycle time. worst case current consumption is shown for both cmos and ttl input levels (commercial temperature range, v cc = 5.5v, 100% duty cycle on chip enable). only standby current is drawn when the chip is disabled. the overall average cu rrent drawn by the stk16c88 depends on the following items: 1. the duty cycle of chip enable 2. the overall cycle rate for accesses 3. the ratio of reads to writes 4. cmos versus ttl input levels 5. the operating temperature 6. the v cc level 7. i/o loading figure 3. current versus cycle time (write) best practices nvsram products have been used effectively for over 15 years. while ease-of-use is one of t he product?s main system values, experience gained working with h undreds of applications has resulted in the following suggestions as best practices: the nonvolatile cells in an nvsram are programmed on the test floor during final test and quality assurance. incoming inspection routines at customer or contract manufacturer?s sites, sometimes, reprogram these values. final nv patterns are typically repeating patterns of aa, 55, 00, ff, a5, or 5a. end product?s firmware should not assume an nv array is in a set programmed state. routines that check memory content values to determine first time system configuration and cold or warm boot status should always program a unique nv pattern (for example, complex 4-byte pattern of 46 e6 49 53 hex or more random bytes) as part of the final system manufacturing test to ensure these system routines work consistently. power up boot firmware routines should rewrite the nvsram into the desired state. while the nvsram is shipped in a preset state, best practice is to again rewrite the nvsram into the desired state as a safeguard against events that might flip the bit inadvertently (program bugs or incoming inspection routines). figure 2. current versus cycle time (read) not recommended for new designs. in production to support ongoing production programs.
stk16c88 document number: 001-50595 rev. *c page 6 of 17 table 1. software store/recall mode selection ce we a 13 ?a 0 mode i/o notes l h 0x0e38 0x31c7 0x03e0 0x3c1f 0x303f 0x0fc0 read sram read sram read sram read sram read sram nonvolatile store output data output data output data output data output data output data [1, 2] l h 0x0e38 0x31c7 0x03e0 0x3c1f 0x303f 0x0c63 read sram read sram read sram read sram read sram nonvolatile recall output data output data output data output data output data output data [1, 2] notes 1. the six consecutive addresses must be in the order listed. we must be high during all six consecutive ce controlled cycles to enable a nonvolatile cycle. 2. while there are 15 addresses on the stk16c88, only the lower 14 are used to control software modes. not recommended for new designs. in production to support ongoing production programs.
stk16c88 document number: 001-50595 rev. *c page 7 of 17 maximum ratings exceeding maximum ratings may shorten the useful life of the device. these user guidelines are not tested. storage temperature .... ............ ............... ?65 ? c to +150 ?c temperature under bias ............ ............... ?55 ? c to +125 ?c supply voltage on v cc relative to gnd .......?0.5 v to 7.0 v voltage on input relative to vss ......... ?0.6 v to v cc + 0.5 v voltage on dq 0?7 ............................... ?0.5 v to v cc + 0.5 v power dissipation ........................................................ 1.0 w dc output current (1 output at a time, 1s duration) .................................. 15 ma operating range range ambient temperature v cc commercial 0 ? c to +70 ? c 4.5 v to 5.5 v industrial ?40 ? c to +85 ? c 4.5 v to 5.5 v dc electrical characteristics over the operating range (v cc = 4.5 v to 5.5 v) parameter description test conditions min max unit i cc1 average v cc current t rc = 25 ns t rc = 45 ns dependent on output loading and cycle rate. values obtained without output loads. i out = 0 ma. commercial ? 97 70 ma ma industrial ? 100 70 ma ma i cc2 average v cc current during store all inputs do not care, v cc = max average current for duration t store ?3m a i cc3 average v cc current at t rc = 200 ns, 5v, 25c typical we > (v cc ? 0.2 v). all other inputs cycling. dependent on output loading and cycle rate. values obtained without output loads. ?10ma i sb1 [3] average v cc current (standby, cycling ttl input levels) t rc = 25 ns, ce > v ih t rc = 45 ns, ce > v ih commercial ? 30 22 ma industrial ? 31 23 ma i sb2 [3] v cc standby current (standby, stable cmos input levels) ce > (v cc ? 0.2 v). all others v in < 0.2v or > (v cc ? 0.2v). ?1.5ma i ix input leakage current v cc = max, v ss < v in < v cc ?1 +1 ? a i oz off state output leakage current v cc = max, v ss < v in < v cc , ce or oe > v ih or we < v il ?5 +5 ? a v ih input high voltage 2.2 v cc + 0.5 v v il input low voltage v ss ? 0.5 0.8 v v oh output high voltage i out = ?4 ma 2.4 ? v v ol output low voltage i out = 8 ma ? 0.4 v note 3. ce > v ih does not produce standby current levels until any nonvolatile cycle in progress has timed out. not recommended for new designs. in production to support ongoing production programs.
stk16c88 document number: 001-50595 rev. *c page 8 of 17 data retention and endurance parameter description min unit data r data retention 100 years nv c nonvolatile store operations 1,000 k capacitance parameter [4] description test conditions max unit c in input capacitance t a = 25 ? c, f = 1 mhz, v cc = 0 to 3.0 v 5 pf c out output capacitance 7pf thermal resistance parameter [4] description test conditions 28-pin pdip unit ? ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/jesd51. tbd ?c/w ? jc thermal resistance (junction to case) tbd ?c/w ac test loads figure 4. ac test loads 5.0 v output 30 pf r1 480 ? r2 255 ? ac test conditions input pulse levels ................................................. 0 v to 3 v input rise and fall times (10%?90%) ....................... < 5 ns input and output timing referenc e levels ..................1.5 v note 4. these parameters are guaranteed by design and are not tested. not recommended for new designs. in production to support ongoing production programs.
stk16c88 document number: 001-50595 rev. *c page 9 of 17 ac switching characteris tics ? sram read cycle over the operating range parameters description 25 ns 45 ns unit min max min max cypress parameter alt parameter t ace t elqv chip enable access time ? 25 ? 45 ns t rc [6] t avav, t eleh read cycle time 25 ? 45 ? ns t aa [7] t avqv address access time ? 25 ? 45 ns t doe t glqv output enable to data valid ? 10 ? 20 ns t oha [7] t axqx output hold after address change 5 ? 5 ? ns t lzce [8] t elqx chip enable to output active 5 ? 5 ? ns t hzce [8] t ehqz chip disable to output inactive ? 10 ? 15 ns t lzoe [8] t glqx output enable to output active 0 ? 0 ? ns t hzoe [8] t ghqz output disable to output inactive ? 10 ? 15 ns t pu [5] t elicch chip enable to power active 0 ? 0 ? ns t pd [5] t ehiccl chip disable to power standby ? 25 ? 45 ns switching waveforms ? sram read cycle figure 5. sram read cycle 1: address controlled [6, 7] figure 6. sram read cycle 2: ce and oe controlled [6] t rc t aa t oha address dq (data out) data valid address t rc ce t ace t lzce t pd t hzce oe t doe t lzoe t hzoe data valid active standby t pu dq (data out) icc notes 5. these parameters are guaranteed by design and are not tested. 6. we must be high during sram read cycles and low during sram write cycles. 7. i/o state assumes ce and oe < v il and we > v ih ; device is continuously selected. 8. measured 200 mv from steady state output voltage. not recommended for new designs. in production to support ongoing production programs.
stk16c88 document number: 001-50595 rev. *c page 10 of 17 ac switching characteris tics ? sram write cycle over the operating range parameters description 25 ns 45 ns unit min max min max cypress parameter alt parameter t wc t avav write cycle time 25 ? 45 ? ns t pwe t wlwh, t wleh write pulse width 20 ? 30 ? ns t sce t elwh, t eleh chip enable to end of write 20 ? 30 ? ns t sd t dvwh, t dveh data setup to end of write 10 ? 15 ? ns t hd t whdx, t ehdx data hold after end of write 0 ? 0 ? ns t aw t avwh, t aveh address setup to end of write 20 ? 30 ? ns t sa t avwl, t avel address setup to start of write 0 ? 0 ? ns t ha t whax, t ehax address hold after end of write 0 ? 0 ? ns t hzwe [8,9] t wlqz write enable to output disable ? 10 ? 15 ns t lzwe [8] t whqx output active after end of write 5 ? 5 ? ns switching waveforms ? sram write cycle figure 7. sram write cycle 1: we controlled [10] figure 8. sram write cycle 2: ce controlled [10] t wc t sce t ha t aw t sa t pwe t sd t hd t hzwe t lzwe address ce we data in data out data valid high impedance previous data t wc address t sa t sce t ha t aw t pwe t sd t hd ce we data in data out high impedance data valid notes 9. if we is low when ce goes low, the outputs remain in the high impedance state. 10. ce or we must be greater than v ih during address transitions. not recommended for new designs. in production to support ongoing production programs.
stk16c88 document number: 001-50595 rev. *c page 11 of 17 autostore or power up recall parameters description stk16c88 unit cypress parameter alt parameter min max t hrecall [11] t restore power up recall duration ? 550 ? s t store t hlhz store cycle duration ? 10 ms t stg [4, 7] power-down autostore slew time to ground 500 ? ns v reset low voltage reset level ? 3.6 v v switch low voltage trigger level 4.0 4.5 v switching waveforms ? auto store or power up recall figure 9. autostore/power up recall v cc v switch v reset power-up recall we dq (data out) autostore ? 5v t hrecall t stg t store brown out au tostorepluse no recall (v cc did not go below v reset ) brown out au tostorepluse recall when v cc returns above v switch power-up recall brown out no store due to no sram writes no recall (v cc did not go below v reset ) note 11. t hrecall starts from the time v cc rises above v switch . not recommended for new designs. in production to support ongoing production programs.
stk16c88 document number: 001-50595 rev. *c page 12 of 17 software controlled store/recall cycle the software controlled store/recall cycle follows. parameters [12, 13] description 25 ns 45 ns unit cypress parameter alt parameter min max min max t rc t avav store/recall initiation cycle time 25 ? 45 ? ns t sa [12] t avel address setup time 0 ? 0 ? ns t cw [12] t eleh clock pulse width 20 ? 30 ? ns t hace [8, 12] t elax address hold time 20 ? 20 ? ns t recall recall duration ? 20 ? 20 ? s switching waveforms ? software controlled store/recall cycle figure 10. ce controlled software store/recall cycle [13] t rc t rc t sa t sce t hace t store / t recall data valid data valid 6 # sserdda 1 # sserdda high impedance address ce oe dq (data) notes 12. the software sequence is clocked on the falling edge of ce without involving oe (double clocking aborts the sequence). 13. the six consecutive addresses must be read in the order listed in the mode selection table. we must be high during all six consecutive cycles. not recommended for new designs. in production to support ongoing production programs.
stk16c88 document number: 001-50595 rev. *c page 13 of 17 ordering code definitions ordering information these parts are not recommended for new designs. they are in production to support ongoing production programs only. speed (ns) ordering code package diagram package type operating range 25 stk16c88-wf25i 51-85017 28-pin pdip industrial 45 stk16c88-wf45 51-85017 28-pin pdip commercial all parts are pb-free. the above table contains final information . please contact your local cypress sales representative for a vailability of these parts speed: 25 - 25 ns 45 - 45 ns package: w = plastic 28-pin 600 mil dip part numbering nomenclature (commercial and industrial) stk16c88 - w f 45 i temperature range: blank - commercial (0 to 70 c) lead finish f = 100% sn (matte tin) i - industrial (?40 to 85 c) not recommended for new designs. in production to support ongoing production programs.
stk16c88 document number: 001-50595 rev. *c page 14 of 17 package diagram figure 11. 28-pin pdip (1.480 0.550 0.1 95 inches) p28.6/pz28.6 pa ckage outline, 51-85017 51-85017 *e not recommended for new designs. in production to support ongoing production programs.
stk16c88 document number: 001-50595 rev. *c page 15 of 17 acronyms document conventions units of measure acronym description ce chip enable cmos complementary metal oxide semiconductor eia electronic industries alliance i/o input/output nvsram non-volatile static random access memory oe output enable pdip plastic dual in-line package sram static random access memory ttl transistor-transistor logic we write enable symbol unit of measure c degree celsius mhz megahertz ? a microampere ? s microsecond ma milliampere ms millisecond ns nanosecond ? ohm % percent pf picofarad v volt w watt not recommended for new designs. in production to support ongoing production programs.
stk16c88 document number: 001-50595 rev. *c page 16 of 17 document history page document title: stk16c88, 256-kbit (32 k 8) autostore+ nvsram document number: 001-50595 rev. ecn no. orig. of change submission date description of change ** 2625096 gvch / pyrs 12/19/08 new data sheet. *a 2826441 gvch 12/11/2009 added contents . updated ordering information (no change in part numbers, only added following text below the heading ?these parts are not recommended for new designs. they are in production to support ongoing production programs only.?) added watermark in pdf stating ?not recommended for new designs. in production to support ongoing production programs only.? *b 3052511 gvch 10/08/10 updated ordering information (removed the following inactive parts: stk16c88-wf25, STK16C88-WF45I). updated package diagram . *c 3536182 gvch 02/27/2012 updated package diagram . added acronyms and units of measure . updated in new template. not recommended for new designs. in production to support ongoing production programs.
document number: 001-50595 rev. *c revised february 27, 2012 page 17 of 17 all products and company names mentioned in this document may be the trademarks of their respective holders. stk16c88 ? cypress semiconductor corporation, 2008-2012. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 not recommended for new designs. in production to support ongoing production programs.

▲Up To Search▲

Price & Availability of STK16C88-WF45I

	To Download STK16C88-WF45I Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .